The present invention relates to a semiconductor device including a SRAM section and a logic circuit section and a manufacturing method thereof.
As is well known, dual gate structures have become a mainstream in the art in association with increases in accuracy of threshold voltages of n-type MIS transistors and p-type MIS transistors which are accompanied by voltage lowering in CMIS (Complementary Metal-Insulator-Semiconductor) devices used in large-scale integrated circuits.
In general, a dual gate structure employs a polysilicon electrode as an n-type gate electrode composing an n-type MIS transistor and a polysilicon electrode as a p-type gate electrode composing a p-type MIS transistor, wherein an n-type impurity is introduced to the n-type gate electrode while a p-type impurity is introduced to the p-type gate electrode. In many cases, the n-type gate electrode and the p-type gate electrode are formed integrally with each other by siliciding the surface of one polysilicon pattern.
Of various methods for introducing a conductive impurity to an n-type gate electrode or a p-type electrode, the conductive impurity is introduced to a polysilicon film before patterning the polysilicon film in some methods, and the conductive impurity is introduced to the n-type gate electrode and the p-type electrode while at the same time being introduced to source/drain regions in other methods. In both cases, thermal treatment is performed after implantation of the conductive impurity for promoting mutual diffusion of an n-type impurity in the n-type gate electrode and a p-type impurity in the p-type electrode in the integrally-formed n-type and p-type gate electrodes.
In order to reduce power consumption and cost, miniaturization of semiconductor devices and improvement on transistor characteristics are progressing more and more.
Referring to, for example, a semiconductor device including a SRAM section and a logic circuit section, it is demanded for further miniaturization of the semiconductor device to reduce a width of an element isolation region that electrically separate an n-type MIS transistor and a p-type MIS transistor in the SRAM section to the limit on the level that can secure the element isolation characteristics.
On the other hand, in the logic circuit section, which determines the operation speed of the semiconductor device, it is demanded to reduce the thickness of the gate insulating film composing respective conductivity type MIS transistors.
The use of a SiON film as the gate insulating film for thickness reduction thereof for the purpose of improving the transistor characteristics involves problems on reliability, such as TDDB (Time Dependent Dielectric Breakdown), and the like.
Alternatively, the use of a high-k film, such as a HfSiON, film or the like, which can achieve electrical reduction in thickness of the gate insulating film rather than physical reduction therein, involves difficulty in control on threshold voltages of the transistors.
In view of the foregoing, in order to achieve electrical reduction in thickness of the gate insulating film in the case employing a combination of, for example, polysilicon electrodes and an insulating film formed of a SiON film, the impurity concentrations of the gate electrodes are increased in some methods.
In addition, in the case employing a combination of, for example, metal gate electrodes and a gate insulating film formed of a SiON film or a high-k film, the impurity concentrations of the gate electrodes are increased in some methods for controlling the threshold voltage of the transistors.
Nevertheless, the following problems are involved in the semiconductor devices including the gate electrodes of which impurity concentrations are increased for the purpose of electrical reduction in thickness of the gate insulating film or control on the threshold voltages of the transistors. The problems in the semiconductor device will be described as a conventional example with reference to FIG. 6A to FIG. 6C and FIG. 7A to FIG. 7B. FIG. 6A to FIG. 6C and FIG. 7A to FIG. 7B are sectional views of a main part in the gate width direction of the semiconductor device for showing respective steps of a semiconductor device manufacturing method in the conventional example.
First, as shown in FIG. 6A, element isolation regions 301 formed of silicon oxide films buried in trenches are formed selectively in upper parts of a semiconductor substrate 300 made of p-type silicon by shallow trench isolation (STI). Then, a SRAM section n-type well region 302 is formed in a p-type MIS formation region of the semiconductor substrate 300 in the SRAM section while a logic circuit section n-type well region 303 is formed in a p-type MIS formation region of the semiconductor substrate 300 in the logic circuit section.
Next, a SRAM section gate insulating film 304 formed of a silicon oxynitride (SiON) film having a thickness of 1.7 nm is formed in a region surrounded by the element isolation regions 301 of the semiconductor substrate 300b in the SRAM section while a logic circuit section gate insulating film 305 formed of a SiON film having a thickness of 1.7 nm is formed in a region surrounded by the element isolation regions 301 of the semiconductor substrate 300 in the logic circuit section. Then, low pressure CVD is performed to form a gate electrode formation film 306 formed of a polysilicon film having a thickness of 100 nm on the entirety of the semiconductor substrate 300.
Subsequently, as shown in FIG. 6B, an n-type impurity, such as phosphorous or the like is implanted to the gate electrode formation film 306 on each of the n-type MIS formation regions in the SRAM section and the logic circuit section with a resist pattern 307 having openings in parts corresponding to the n-type MIS formation regions in the SRAM section and the logic circuit section as a mask to form a SRAM section n-type gate electrode formation film 308 and a logic circuit section n-type gate electrode formation film 309. Then, the resist pattern 307 is removed.
Thereafter, as shown in FIG. 6C, a p-type impurity, such as boron or the like is implanted to the gate electrode formation film 306 on each of the p-type MIS formation regions in the SRAM section and the logic circuit section with the use of a resist pattern 301 having openings in parts corresponding to the p-type MIS formation regions in the SRAM section and the logic circuit section as a mask to form a SRAM section p-type gate electrode formation film 311 and a logic circuit section p-type gate electrode formation film 312. Then, the resist pattern 310 is removed.
Referring herein to the case employing a combination of polysilicon electrodes and a gate insulating film made of a SiON, when the impurity concentration of an n-type gate electrode composing an n-type MIS transistor is increased, the transistor characteristics of the n-type MIS transistor is improved effectively. In contrast, even when the impurity concentration of a p-type gate electrode composing a p-type MIS transistor is increased, the transistor characteristics of the p-type MIS transistor is not improved and the reliability of the gate insulating film composing the p-type MIS transistor may lower.
To tackle this problem, conditions for implanting phosphorous in the step of implanting the n-type impurity to the n-type gate electrode formation films 308, 309 (see FIG. 6B) and conditions for implanting boron in the step of implanting the p-type impurity to the p-type gate electrode formation films 311, 312 (see FIG. 6C) are adjusted so that the phosphorous concentration of the n-type gate electrode formation films 308, 309 is two times or more the boron concentration of the p-type gate electrode formation films 311, 312.
Next, as shown in FIG. 7A, patterning is performed on the SRAM section n-type gate electrode formation film 308, the SRAM section p-type gate electrode formation film 311, the logic circuit section n-type gate electrode formation film 309, and the logic circuit section p-type gate electrode formation film 312 to form a SRAM section n-type gate electrode 308A, a SRAM section p-type gate electrode 311A, a logic circuit section n-type gate electrode 309A, and a logic circuit section p-type gate electrode 312A. Wherein, the SRAM section n-type gate electrode 308A is formed integrally with the SRAM section p-type electrode 312A while the logic circuit section n-type gate electrode 309A is formed integrally with the logic circuit section p-type gate electrode 312A, as shown in FIG. 7A.
Subsequently, as shown in FIG. 7B, extension regions (not shown), sidewalls (not shown), and source/drain regions (not shown) which compose the respective conductivity type MIS transistors are formed by known techniques self-alignedly.
In thermal treatment, such as annealing for activating the source/drain regions and the like, the phosphorous in the SRAM section n-type gate electrode 308A and the boron in the SRAM section p-type gate electrode 311A diffuse mutually in the integrally-formed n-type and p-type gate electrodes 308A, 311A in the SRAM section. As well, the phosphorous in the logic circuit section n-type gate electrode 309A and the boron in the logic circuit section p-type gate electrode 312A diffuse mutually in the integrally-formed n-type and p-type gate electrodes 309A, 312A in the logic circuit section.
The diffusion rate of phosphorous is higher than the diffusion rate of boron in general. Therefore, the amount of the phosphorous that diffuses from the respective n-type gate electrodes 308A, 309A toward the respective p-type gate electrodes 311A, 312A is larger than the amount of the boron that diffuses from the respective p-type gate electrodes 311A, 312B toward the respective n-type gate electrodes 308A, 309A.
For this reason, the pn boundary between the SRAM section n-type gate electrode 308A and the SRAM section p-type gate electrode 311A shifts toward the SRAM section p-type gate electrode 311A (see an arrow Ds in FIG. 7B) while the pn boundary between the logic circuit section n-type gate electrode 309A and the logic circuit section p-type gate electrode 312A shifts toward the logic circuit section p-type gate electrode 312A (see an arrow D1 in FIG. 7B)
Thus formed on the semiconductor substrate 300 in the SRAM section are, as shown in FIG. 7B: a SRAM section n-type MIS transistor including the SRAM section n-type gate electrode 308B formed with the SRAM section gate insulating film 304 interposed and a SRAM section p-type MIS transistor including the SRAM section p-type gate electrode 311B formed with the SRAM section gate insulating film 304 interposed. As well, there are formed on the semiconductor substrate 300 in the logic circuit section: a logic circuit section n-type MIS transistor including the logic circuit section n-type gate electrode 309B formed with the logic circuit section gate insulating film 305 interposed and a logic circuit section p-type MIS transistor including the logic circuit section p-type gate electrode 312B with the logic circuit section gate insulating film 305 interposed.
In the semiconductor device in the conventional example, as shown in FIG. 7B, in the SRAM section, which is comparatively small in width of the element isolation between the n-type MIS transistor and the p-type MIS transistor, the pn boundary between the SRAM section n-type gate electrode 308B and the SRAM section p-type gate electrode 311B shifts over the element isolation region 301 to reach a point on the SRAM section gate insulating film 304 located on the SRAM section n-type well region 302. This disables securing of the transistor characteristics of the SRAM section p-type MIS transistor.
On the other hand, as shown in FIG. 7B, in the logic circuit section, which is comparatively large in width of the element isolation between the n-type MIS transistor and the p-type MIS transistor, the pn boundary between the logic circuit section n-type gate electrode 309B and the logic circuit section p-type gate electrode 312B remains on the element isolation region 301.
Particularly, in the case employing a combination of polysilicon electrodes and a gate insulating film made of SiON, the n-type gate electrode formation films 308, 309 are formed so as to have high phosphorous concentration (two times or more the boron concentration of the p-type gate electrode formation films 311, 312, for example) for the purpose of improving the transistor characteristics of the n-type MIS transistors, and therefore, the amount of phosphorous that diffuses from the respective n-type gate electrodes 308A, 309a toward the respective p-type gate electrodes 311A, 312A may be more larger than the amount of boron that diffuses from the respective p-type gate electrodes 311A, 312A toward the respective n-type gate electrodes 308A, 309A.
For this reason, in the SRAM section of the semiconductor device of the conventional example, which is comparatively small in width of the element isolation between the n-type MIS transistor and the p-type MIS transistor, the width of the element isolation must be increased to prevent the pn boundary between the SRAM section n-type gate electrode 308B and the SRAM section p-type gate electrode 311B from reaching a point on the SRAM section gate insulating film 304 located on the SRAM section n-type well region 302.
However, when the width of the element isolation between the SRAM section n-type MIS transistor and the SRAM section p-type MIS transistor is increased for the purpose of securing the transistor characteristics of the SRAM section n-type MIS transistor and the SRAM section p-type MIS transistor, the SRAM section increases in area to increase the area of the semiconductor chip.
In sum, in the semiconductor device of the conventional example, though the transistor characteristics of the logic circuit section n-type MIS transistor and the logic circuit section p-type MIS transistor can be improved, the transistor characteristics of the SRAM section n-type MIS transistor and the SRAM section p-type MIS transistor cannot be improved and secured on the contrary. In addition, in order to secure the transistor characteristics of the SRAM section n-type MIS transistor and the SRAM section p-type MIS transistor in the semiconductor device of the conventional example, the width of the element isolation between the SRAM section n-type MIS transistor and the SRAM section p-type MIS transistor must be increased.